Semiconductor networks



Oct. 12, 1965 s. KlLBY ETAL 3,211,972

SEMICONDUCTOR NETWORKS Original Filed Feb. 6, 1961 2 Sheets-Sheet 1 /5 wP/P/O/P 14/?7 \l k L l 2 2/ INVENTORS Jae/c S. Kzidbg, Jay M Lat/amp BYa B ATTORNEYS Oct 1 1 J. s. KlLBY ETAL SEMICONDUCTOR NETWORKS 2Sheets-Sheet 2 Original Filed Feb. 6, 1961 Ma h INVENTORS Jae/c 6.Kz'iby, Jay M Laikrqp BY \w 7:) 2M

ATTORNEYS United States Patent 3,211,972 SEMICONDUCTOR NETWORKS Jack S.Kilby and Jay W. Lathrop, Dallas, Tex., assignors to Texas InstrumentsIncorporated, Dallas, Tex., a corporation of Delaware Continuation ofapplication Ser. No. 87,258, Feb. 6, 1961.

This application June 24, 1964, Ser. No. 377,710 7 Claims. (Cl. 317-235)This invention relates to single crystal semiconductor networks, andmore particularly to semiconductor networks which include as an integralpart an epitaxial semiconductor layer.

This application is a continuation of our copending application, SerialNo. 87,258, filed Feb. 6, 1961, now abandoned.

In modern-day electronic packaging, the need for small as well aslight-weight electronic devices has become critical. The discovery ofthe various semiconductor devices such as the transistor and the tunneldiode has made it possible for circuit designers to achieve componentdensities several orders of magnitude higher than was possible using thevacuum tube circuit components. However, in many applications the sizeand weight of many electronic systems utilizing the semiconductordevices is much greater than is desired or can be tolerated.

In the co-pending application of Jack S. Kilby, Serial No. 791,602,there is disclosed a unique integrated electronic circuit fabricatedfrom single crystal semiconductor material. As described in thisco-pending application, circuit modules comprising several differentcircuit components such as transistors, diodes, resistors and capacitorsare fabricated from a single crystal semiconduc' tor structure. Thesecircuit modoules are referred to as semiconductor networks and for thepurposes of this application a semiconductor network is defined as asingle crystal semiconductor structure including at least twointerconnected circuit components of different types.

The discovery of these semiconductor networks constituted a majorbreakthrough in the field of circuit miniaturization in that the entireelectronic circuit modules, such as multivibrators, amplifiers oroscillators in a space and of a weight usually allocated to onetransistor are available.

Many of these semiconductor networks, however, fail to function as wellas the same circuit modules comprising individual components andcompromises must be made between the desired reduction in size andweight and the desired circuit characteristics and capabilities. Thereason many of the semiconductor networks of the prior art fail toperform as well as their counterparts made from individual components isthat the components of each semiconductor network are all formed fromthe same single crystal of semiconductor material. The transistors,diodes and capacitors are all made by diffusing impurities into thiscrystal and resistors are made by using the resistivity of thesemiconductor material of this crystal. Thus the originalcharacteristics of this crystal affects the properties of all thecircuit components that are formed therein. The disadvantage of thisfact is that for some components it may be desirable to have onecharacteristic in some portions of the crystal and for others it may bedesirable to have the opposite. For example, for resistors it is usuallydesirable that the resistivity of the semicon- "ice ductor material behigh because higher resistances may be obtained and a given resistancecan be obtained in a shorter dimension. On the other hand, it is usuallydesirable that transistors be formed out of relatively low resistivitymaterial in that in this manner a low saturation voltage is achieved andcollector storage is reduced. When such conflicting desires for thecharacteristics of the crystal of a semiconductor network occur, acompromise must be made resulting in the reduction of the operatingquality of the circuit module.

This problem is overcome according to the concept of the presentinvention by growing an epitaxial layer onto the original singlecrystal. This epitaxial layer will be a continuation of the singlecrystal and its characteristics may be selected to be whatever isdesired. Thus its resistivity may be selected to be much lower than thatof the original crystal portion and the transistors of a semiconductornetwork may be formed in this layer while the high resistance originalmaterial can be used to provide the resistors. This technique of growingan epitaxial layer also permits heavier doped regions: to be buriedbeneath more lightly doped regions because impurities may be diffused inregions of the original material before the epitaxial layer is grown.This feature enables much higher resistivity material to be used to formthe resistors than was heretofore practical because of the difliculty ingetting a good ohmic contact with high resistivity semiconductormaterial. A good ohmic contact can be obtained to high resistivitysemiconductor material by the use of a low resistivity epitaxial layergrown on top of a heavily doped region in the high resistivitysemiconductor material.

It is therefore the principal object of this invention to provideimproved semiconductor networks.

It is another object of this invention to incorporate an epitaxialregion as part of a semiconductor network.

It is a further object of this invention to permit more selectivity ofthe characteristics of different regions of a semiconductor network.

It is a still further object of this invention to permit heavier dopedregions to be buried under more lightly doped regions.

It is a still further object of this invention to make possible the useof very high resistivity material for one part of a semiconductornetwork while using a very low resistivity material for another part ofa semiconductor network.

It is a still further object of this invention to facilitate theobtaining of a good ohmic contact to high resistivity semiconductormaterial.

Further objects and advantages of the present invention will becomeapparent as the following detailed description of preferred embodimentsof the invention unfold and when taken in conjunction with the drawings,wherein:

FIGURE 1 shows in cross section a semiconductor network of the priorart;

FIGURE 2 is a diagram of a circuit provided by the semiconductor networkof FIGURE 1;

FIGURE 3 is a cross-sectional showing of an intermediate stage in themanufacture of a semiconductor network according to the concept of thepresent invention providing the circuit of FIGURE 2;

FIGURE 4 is a view in perspective of a semiconductor network accordingto the present invention providing the circuit of FIGURE 2; i

FIGURE is a cross section through the semiconductor network of FIGURE 4along the lines 5-5;

FIGURE 6 illustrates in cross section a semiconductor network of theprior art providing a three-way AND ate; g FIGURE 7 is a diagram of thecircuit provided by the semiconductor network of FIGURE 6;

FIGURE 8 is a cross-sectional showing of an intermediate stage in themanufacture of a semiconductor network according to the presentinvention providing the circuit of FIGURE 7;

FIGURE .9 is a view in elevation of a semiconductor network according tothe present invention providing the circuit of FIGURE 7; and

FIGURE a cross section through the semiconductor network of FIGURE 9along the lines 1010.

The semiconductor network of the prior art illustrated .in FIGURE 1comprises a single crystal 11 of relatively high resistivitysemiconductor material such as silicon. In the illustrative example ofFIGURE 1 the crystal 11 has an N-type conductivity and a resistivity of10 ohm-centimeters. At one end of the block 11 a region 13 of P-typeconductivity is formed by solid state diffusion and a heavily dopedregion 15 of N-type conductivity is formed by solid state diffusion inthe region 13. The top of the block 11 is etched to leave a mesa 16including the region 13 and the region 15 projecting up from the mainbody of the block 11. The PN junctions between the N-type conductivityregion 15 and the remaining P-type conductivity material of the region13 and between the remaining N-type conductivity material of the block11 and the P- type conductivity material of the region 13 form an NPNtransistor in the mesa 16 with the P-type conductivity material of theregion 13 providing the base, the region 15 providing the emitter andthe remaining N-type conductivity material of the block 11 providing thecollector.

An ohmic contact 17 is provided to the P-type conductivity material ofthe region 13 and acts as the base elec trode of the transistor. Anohmic contact 21 to the block 11 directly beneath the mesa 16 providesthe collector electrode of the transistor, and an ohmic contact 23 tothe heavily doped region 15 provides the emitter electrode of thetransistor. At the opposite end of the block 11 from the mesa 16, anohmic contact 19 is provided. The relatively high resistivity materialbetween the contacts 19 and 21 in the block 11, in effect, provides aresistor connected to the collector of the transistor in the mesa 16.

FIGURE 2 illustrates schematically the circuit provided by thesemiconductor network of FIGURE 1. As shown in FIGURE 2, a resistor 25is connected between a terminal 18 and the collector of an NPNtransistor 27. A terminal 24 is connected to the emitter of thetransistor 27, a terminal 22 is connected to the base of the transistor27, and a terminal 20 is connected to the collector of the transistor27, or in other words to the junction between the resistor and thecollector of the transistor 27. The resistor 25 is provided by theresistivity of the semiconductor material between contacts 19 and 21 andthe transistor 27 is provided by the transistor of the mesa 16. Theterminals 18, 20, 22 and 24 are provided by the contacts 19, 21, 17 and23 respectively. Because of the difficulty of forming ohmic contacts onhigh resistivity material, as a practical matter the resistivity of theblock 11 is limited to 10 ohm-centimeters. As a result, the resistor 25provided by the block 11 has a maximum value of 40,000 ohms in apractical embodiment of this semiconductor network. Furthermore, the useof material of even this high resistivity in the block 11 has resultedin several serious compromises in the design of the transistor 27.Because the relatively high resistivity material of the block 11provides the collector of the transistor 27, the transistor 27 will havea relatively high value of saturation voltage. This high saturationvoltage is undesirable, particularly when the transistor 27 is to beused in a switching application. For in a switching application it is desired that when the transistor 27 is conducting or turned on, thetransistor will act as nearly as possible as a short circuit. Becausethe transistor 27 has a relatively high saturation voltage, it will havea relatively high voltage between its collector and emitter when it isconducting or turned on and thus, will not approach the desired shortcircuit. Furthermore, the relative high resistivity of the collector ofthe transistor 27 provided by the block 11 also permits increasedcollector storage, which results in a considerably slower switching timefor the device.

The present invention enables the circuit of FIGURE 2 to be provided bya semiconductor network in which a much higher resistivity materialprovides the resistor 25, thus obtaining a much higher resistance forthe resistor 25, whereas the collector region of the transistor 27 isprovided by a much lower resistivity material. The improvedsemiconductor network providing the circuit of FIGURE 2 according to thepresent invention is illustrated in FIGURES 3 through 5.

As shown in FIGURE 3, which illustrates the semiconductor network in anintermediate stage of manufacture, a high resistivity single crystal ofsemiconductor material in wafer form designated by the reference number29 is provided. In the embodiment of FIGURES 35, the wafer 29 will havea resistivity of I00 ohm-centimeters and is of N-type conductivity. Twoheavily doped N-type regions 31 and 32 (about 0.1 ohm-centimeter orless) are diffused into the top surface of the wafer 29 at opposite endsthereof. On top of the wafer 29 an epitaxial layer 33 of semiconductormaterial is grown. The layer 33 will be a continuation of the singlecrystal, which is essential. One way to produce this epitaxial layer isto vapor deposit semiconductor material on the crystal wafer 29 inaccordance with the disclosure in Epitaxial Growth of Silicon by Wajdaet al. IBM Journal of Research and Development, 4, pages 288295 (1960)and Impurity Introduction During Epitaxial Growth of Silicon by Glang eta.l IBM Journal of Research and Development, 4, pages 299-301 (1960).The characteristics, including the resistivity and the conductivity typeof the epitaxial layer, can be freely selected. In the embodiment ofFIGURE 3 the conductivity is selected to be of N-type and theresistivity is selected to be relatively low, and preferably between 0.5and 1.0 ohm-centimeter. A P-type region 35 is formed in the N-typeepitaxial layer 33 by solid state diffusion. This region 35 is formedover the heavily doped N-type region 31 in the wafer 29. A heavily dopedN-type region 37 is formed in the P-type region 35 by solid statediffusion. Also a heavily doped N-type region 39 is formed in the N-typematerial of the layer 33 alongside of the region 35 by solid statediffusion and a heavily doped N-type region 41 is formed in the layer 33over the N-type region 32 by solid state diffusion. The epitaxial layer33 is then etched to leave the mesas designated generally in FIG- URES 4and 5 by the reference numbers 43 and 45. The layer 33 is etchedentirely away so that the mesas 43 and 45 are joined only by the highresistivity material of the wafer 29. The etching is carried out so thatthe mesa 43 contains the P-type region 35 with the N-type region 37therein and also the heavily doped N-type region 39 and the mesa 45contains the heavily doped N-type region 41. The regions in the mesa 43form a transistor with the N-type region 37 providing the emitter, theP- type material of the region 35 providing the base, and the remainingN-type material of the layer 33 in the mesa 43 providing the collector.The heavily doped N-type region 39 in the mesa 43 is used to provide acontact to the collector of the transistor. An ohmic contact 49 is madeto the heavily doped N-type region 37 to provide the emitter electrode,an ohmic contact 47 is made to the remaining P-type material in theregion 35 to provide the base electrode, and an ohmic contact 48 is madeto the region 39 to provide the collector electrode. An ohmic contact 50is made to the heavily doped region 41. This semiconductor network shownin FIGURES 4 and 5 will provide the circuit illustrated in FIGURE 2 withthe mesa 43 providing the transistor 27 and with the semiconductormaterial between the mesas 45 and 43 providing the resistor 25. Theterminals 18, 20, 22 and 24 are provided by the contacts 50, 48, 47 and49, respectively. Because high resistivity material is used for thewafer 29, the resistance of the resistor 25 may be made much higher andalso the wafer 29 does not have to be made nearly as long to provide anadequately high resistance. Furthermore, the resistivity of thecollector region of the transistor 27 is substantially reduced sincethis collector region is provided by the epitaxial layer 33 which has arelatively low resistivity. Thus, the transistor 27 will have a lowsatura tion voltage permitting it to act more as a short circuit when itis switched on and also it will have greatly reduced collector storageresulting in a much faster switching time for the transistor 27.Furthermore, the provision of the heavily doped region 41 in the lowresistivity epitaxial layer in the mesa 45 formed on the heavily dopedregion 32 in the high resistivity base permits a good ohmic contact tothe high resistivity material. Similarly, the heavily doped region 31makes a good ohmic contact between the collector region of thetransistor and the high resistivity material of the wafer 29 and alsolimits depletion layer width in the collector noticeably improvingswitching characteristics of transistor. Thus, all of the problemsdiscussed above associated with the semiconductor network of the priorart illustrated in FIGURE 1 are overcome by the use of the epitaxiallayer 33 in forming the semiconductor network.

As illustrated in FIGURE 3, the epitaxial layer permits a heavily dopedreigon such as the regions 31 and 32 to be completely surrounded in asingle crystal structure by material that is more lightly doped. In theembodiment in FIGURES 4 and 5, these buried regions 31 and 32 permitgood ohmic contact to be made to the high resistivity material of thewafer 29. It will be obvious that this structure will have many otherapplications in semiconductor networks and the achievement of thisstructure vastly widens the horizon in the technology of this field. InFIGURE 6 there is illustrated another semiconductor network of the priorart. This semiconductor network comprises an AND gate, the circuit ofwhich is shown in FIGURE 7. The semiconductor network of FIGURE 6comprises a single crystal block 51 of semiconductor material of P-typeconductivity. Near one end of this block three regions of N-typeconductivity are formed by solid state diffusion. These three regionsare designated by the reference numbers 53 through 55 in FIGURE 6. Thejunction between the regions of N-type material 53 through 55 and theP-type material of the block 51 form semiconductor diodes. An ohmiccontact '56 is made to the block 51 beneath the regions 53 through 55and an ohmic contact 57 is made to the opposite end of the base 51.Ohmic contacts 52, 58 and 62 are made to the N-type regions 53, 54 and55, respectively. The resistivity of the block 51 between the ohmic con-.tacts 57 and 56 provides a resistor. Thus, the semiconductor networkshown in FIGURE 6 provides an AND gate, the, circuit of which isillustrated in FIGURE 7. In this circuit a resistor 63 is connectedbetween a terminal 64 and three diodes 59 through 61, which connect theresistor 63 to terminals 65 through 67, respectively. A terminal 68 isconnected to the junction between the diodes 59 through 61 and theresistor 63. The three diodes 59 through 61 are the diodes formed by thejunctions of the N-type regions 53 through 55 with the P-type materialof the block 51 and the resistance 63 is provided by the resistivity ofthe block 51 between the contacts 57 and 56. The terminals 64 through 68are provided by the contacts 57, 62, 58, 52 and 56 respectively. Thus,

the semiconductor network shown in FIGURE 6 provides a three input ANDgate.

As in the case with the transistor-resistor combination, the AND gate ofFIGURE 6 has the limitation that the resistivity of the P-type materialof the block 51 cannot be made very high because the ohmic contacts 56and 57 must be formed therewith, and as pointed out above it is verydifiicult to get a good ohmic contact to high resistivity material.Furthermore, if the resistivity of the material of the block 51 is madetoo high, the diodes 59 through 61 in the circuit of FIGURE 7 will, ineffect, instead of having a direct connection to the resistor 63, eachbe connected to the resistor 63 through a series resis tor. With suchseries resistors included in the circuit of FIGURE 7 the operation ofthe circuit as an AND gate would be seriously impaired. Therefore, toget an adequately high resistance for the resistor 63, the block 51 mustbe made relatively long.

With the concept of the present invention of making part of thesemiconductor network, an epitaxial layer which is grown on an originalsingle crystal, these prob lems can be overcome. FIGURES 810 illustratea semiconductor network according to the present invention providing theAND gate of FIGURE 7.

FIGURE 8 illustrates an intermediate stage in the manufacture of thissemiconductor network. As shown in FIGURE 8 a single crystal wafer 71having a high resistivity and a P-type conductivity is provided. On eachside of this wafer, heavily doped N-type regions 73 and 75 (about 0.1ohm-centimeter or less) are formed by solid state diffusion. Then on topof the heavily doped regions 73 and 75, on each side of the wafer 71,epitaxial layers 77 and 79 are grown. These epitaxial layers are ascontinuations of the semiconductor single crystal structure, selected tohave relatively low resistivities, and to be of P-type conductivity. Inthe epitaxial layer 79 a plurality of small regions of N-type materialare formed by solid state difiusion. These regions 81 are arranged ingroups of three. With each group of three regions 81 of N-type materiala region 82 of heavily doped P-type material is formed by solid statedifiusion. The structure of FIG URE 8 is then diced so that each groupof three regions 81 with one region 82 will be in a separate crystalportion. FIGURES 9 and 10 illustrate one of the portions resulting afterthe dicing operation. As shown in these figures, the crystal portion orunit comprises a bar of semiconductor material at the ends of which areepitaxial layers 91 and 93 of P-type material. Between the epitaxiallayers 91 and 93 is a bar 95 of high resistivity P-type material. Theepitaxially grown layers 91 and 93 are joined to the high resistivityP-type material by the heavily doped regions 97 and 99. In the epitaxiallayer 93 are three regions of N-type material 81 and one region 82 ofheavily doped P-type material. The three regions 81 of N-type materialform three diodes with the P-type material of the epitaxial layer 93. Aregion 92 of heavily doped P-type material is formed in the epitaxiallayer 91 by solid state diffusion. Ohmic contacts 94 are made to theN-type regions 81, an ohmic contact 98 is made to the heavily dopedP-type region 82, and an ohmic contact 96 is made to the heavily dopedP-type region 92. This structure shown in FIGURES 9 and 10 will providethe AND gate circuit shown in FIGURE 7. The diodes 59 through 61 areprovided by the junctions between the N-type regions 81 and theepitaxial layer 93 of P-type material and the resistor 63 is provided bythe high resistivity P-type material between the epitaxial layers 93 and91. The terminals 65 through 67 are provided by the contacts 94, theterminal 68 is provided by the contact 98, and the terminal 64 isprovided by the contact 96. Because the resistor 63 is provided by ahigh resistivity material, it is possible to form it with such a shortlength of the material that the Width of a semiconductor wafer issufficient. For this reason the AND gates may be produced by dicing aWafer in the manner described with reference to FIGURE 8. The fact thatthe epitaxial layers 93 and 91 are provided on each end of the highresistivity bar 95 permits these regions 91 and 93 to be of lowresistivity. Thus, virtually no resistance will appear between thediodes 59 through 61 and the resistor 63 in the circuit of FIGURE 7 andgood ohmic contacts are made to the high resistivity bar 95. With somecrystal growing processes it may be desirable to grow only layer 93 andto form the region 92 by diffusing directly into layer 95.

If further increases in transistor speed are required in semiconductornetworks, the epitaxial layer can be doped during its growth with alifetime killing agent such as gold. Doping during growth provides anearly constant dope level throughout the epitaxial layer. This is agreat improvement over the error function distribution currentlyobtained by conventional solid state diffusion processes. This techniqueis also of considerable value for individual transistors as well assemiconductor networks.

From the above description of the invention it will be seen that thebasic concept of the applicants invention is making use of an epitaxiallayer as an integral part of a semiconductor network. The techniques ofthe present invention are applicable to many semiconductor networksother than those described above and many modifications may be made tothese specific embodiments without departing from the spirit and scopeof the invention.

What is claimed is:

1. An integrated circuit comprising a monocrystalline semiconductorsubstrate, a layer of epitaxial semiconductor material overlying atleast a portion of one face of the substrate, a circuit componentdefined in a part of the epitaxial layer by thin, limited area,surface-adjacent regions of alternate conductivity type, and means formaking low resistance electrical connection to a portion of theepitaxial layer which underlies said regions, said means comprising aheavily doped layer of the semiconductor material interposed between theepitaxial layer and the substrate, and a contact on the top surface ofthe epitaxial layer above a part of the heavily doped layer.

2. In a semiconductor device of the type having diverse circuitcomponents in a monocrystalline body of semiconductor material, asemiconductor substrate heavily doped semiconductor material of oneconductivity type at one face of the substrate, epitaxially-grownsemiconductor material of said one conductivity type overlying theheavily doped semiconductor material on said one face of the substrate,substantial electrical impedance being exhibited through the bodybetween portions of the heavily-doped semiconductor material and betweenportions of the epitaxially-grown semiconductor material, a circuitcomponent formed in the surface of at least one of such portions of theepitaxially-grown semiconductor material by r thin, limited area,regions of alternate conductivity-type, and a low resistance connectionto the portion of the epitaxially-grown region subjacent said regions,said low resistance connection comprising a contact on theepitaxially-grown region at said one face spaced from said regions and alow resistance path through the heavily doped semiconductor materialsubjacent said portion.

3. A transistor comprising a monocrystalline semiconductor substrate, aheavily doped layer of monocrystalline semiconductor material of oneconductivity type adjacent one face of the substrate, an epitaxiallygrown region of monocrystalline semiconductor material of said oneconductivity type on said one face overlying said heavily doped layer, abase region of the opposite conductivity 0 region with a low resistancepath to said portion being provided in a direction generally parallelwith said one face by said heavily doped layer.

4. A transistor comprising a semiconductor substrate, a heavily dopedlayer of monocrystalline semiconductor material of one conductivity typeadjacent one face of the substrate, a lightly doped region ofmonocrystalline semiconductor material of said one conductivity type onsaid one face overlying said heavily doped layer, a base of the oppositeconductivity type formed in said region above said heavily doped layerbut spaced therefrom, the portion of said region immediately underlyingsaid base providing the collector of the transistor, and emitter of saidone conductivity type on said one face formed in said base above saidportion of said region but spaced therefrom, separate electricalcontacts to the emitter and base on said one face, and a collectorconnection on said one face comprising a contact overlying said regionwith a low resistance path to said portion being provided in a directiongenerally parallel with said one face by said heavily doped layer.

5. In an integrated circuit, a semiconductor substrate, a layer ofepitaxial semiconductor material overlying at least a portion of oneface of the substrate, a circuit component defined in a part of theepitaxial layer and including thin surface-adjacent regions of alternateconductivity type, and means for making low resistance electricalconnection to a portion of the epitaxial layer which underlies saidregions, said means comprising a heavily doped layer of thesemiconductor material interposed between the epitaxial layer and thesubstrate, and a contact on the top surface of the epitaxial layer abovea part of the heavily doped layer.

6. In a semiconductor device of the type having diverse circuitcomponents in a unitary structure, a semiconductor substrate, heavilydoped semiconductor material of one conductivity type adjacent one faceof the substrate, relatively lightly doped semiconductor material ofsaid one conductivity type overlying the heavily doped semiconductormaterial adjacent said one face of the substrate, substantial electricalimpedance being exhibited through the substrate between portions of theheavily doped semiconductor material and between portions of the lightlydoped semiconductor material, a circuit component formed in the surfaceof at least one of such portions of the lightly doped semiconductormaterial by thin, limited-area, regions of alternate conductivity type,and a low resistance connection to the portion of the lightly dopedregion subjacent said regions of alternate conductivity type, said lowresistance connection comprising a contact on the lightly doped regionadjacent said one face spaced from said regions of alternateconductivity type and a low resistance path through the heavily dopedsemiconductor material subjacent said portion.

7. In a semiconductor device of the type having diverse circuitcomponents in a unitary structure: a substrate composed of highresistance silicon and having a major face, a plurality ofmonocrystalline regions of relatively lightly doped silicon of one typeconductivity adjacent said major face, relatively heavily doped siliconof said one type adjacent said major face interposed between saidregions and said substrate, substantial electrical impedance beingexhibited through the substrate between portions of the heavily dopedsilicon and between regions of the lightly doped silicon, a transistorformed in the surface of one of the regions of lightly doped silicon bya thin base region of the opposite type and a thin emitter region ofsaid one type, separate electrical connections to the base andemitterregions on said major face, the portion of said region of lightly dopedsilicon immediately underlying said base region providing the collectorof the transistor, and a collector connection on said major havecomprising a contact overlying said region of lightly doped 9 10 siliconspaced from said base region with a low resistance OTHER REFERENCES pathto said collector being provided in a direction gen- Theuerer et aL:Article in Proceeding of the IRE, Sept erally parallel to said majorface by said heavily doped 1, 1960, Pages 1642 1643 slhcon' Van Ligten:Epitaxially Diffused Transistor Fabrica- 5 tion, IBM TechnicalDisclosure Bulletin, vol. 4, No. 10, References Cited by the ExaminerMarch 1962, pages 5849.

UNITE-D STATES PATENTS IN, P E m' er. 3,089,794 5/63 Marinace 148-175DAVID J GALV W m 3,149,395 9/64 Bray et a1. 29 25.3 DAVID RECK, Exammer-

1. AN INTEGRATED CIRCUIT COMPRISING A MONOCRYSTALLINE SEMICONDUCTORSUBSTRATE, A LAYER OF EPITAXIAL SEMICONDUCTOR MATERIAL OVERLYING ATLEAST A PORTION OF ONE FACE OF THE SUBSTRATE, A CIRCUIT COMPONENTDEFINED IN A PART OF THE EPITAXIAL LAYER BY THIN, LIMITED AREA,SURFACE-ADJACENT REGIONS OF ALTERNATE CONDUCTIVITY TYPE, AND MEANS FORMAKING LOW RESISTANCE ELECTRICAL CONNECTION TO A PORTION OF THEEPITAXIAL LAYER WHICH UNDERLIES SAID REGIONS, SAID MEANS COMPRISING AHEAVILY DOPED LAYER OF THE SEMICONDUCTOR MATERIAL INTERPOSED BETWEEN THEEPITAXIAL LAYER AND THE SUBSTRATE, AND A CONTACT ON THE TOP SURFACE OFTHE EPITAXIAL LAYER ABOVE A PART OF THE HEAVILY DOPED LAYER.